Intel Sees Moore’s Law Continuing Beyond 10nm

[[Coi] Mr.CLuBBeR]

Company believes move to 7nm possible without EUV

We are coming up on the semi-centennial anniversary of Moore’s law, a prediction in 1965 by Intel founder Gordon Moore that the number of transistors on an (economical) integrated circuit would continue to double every 12 months until at least 1975, at which point he revised the rate of “circuit density-doubling” to 24 months. The prediction has held up rather well since then. But with all due respect to its remarkable longevity and massive impact on technology, the many physical limitations to transistor scaling at smaller nodes have led many to conclude the famous axiom is on borrowed time. Intel, however, looks determined to soldier on with Moore’s law beyond the 10nm node.
That’s according to comments made by Mark Bohr, senior fellow for logic technology development at Intel, during a call with reporters to preview the company’s agenda for the 2015 IEEE international Solid-State Circuits Conference (ISSCC) in San Francisco.
Although three of the five papers that the company is scheduled to present at ISSCC deal with existing 14nm process technology, Bohr will take part in a panel discussion on the the move beyond 10nm and the many challenges it poses.
Per existing roadmaps, the company expects to move to 10nm in 2016 and to 7nm in 2018.
"I still believe we can do 7nm without EUV [Extreme Ultraviolet Lithography] and deliver improved cost per transistor. I'm not going to say exactly how, because our competitors watch what we do closely,” Bohr said.
He did drop a few hints, though: "We have published papers on III-V [three-five] devices, so that's one example [of the new materials Intel could use to move to 7nm], but introducing any new technology will be about balancing performance against manufacturability [sic]."
Bohr’s comments assume significance because EUV, for long considered the best bet to replace current 193-nm lithography and extend Moore’s law beyond 10nm, isn’t ready for prime time — in fact, hasn’t been for over a decade now.
"Scaling does continue to provide lower cost per transistor, and it is Intel's view that cost reduction is needed to justify new generations of process technology," he said, adding that it is crucial to recognize the importance of heterogeneous integration.

"Going forward, heterogeneous integration will become increasingly important, but we may not be able to do it all on one chip, so you will see more use of SoC solutions such as 2.5D integration, where two are mounted side by side on a substrate, or full 3D integration, stacking chips on top of each other, each one tuned for a different [manufacturing] process to perform different functions.”
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